Generally speaking, there are two principal areas of concern in semiconductor device technology--namely, conveying signals and currents into and within a semiconductor die, and processing the signals within the die. The present invention concerns itself with conveying signals and currents from sources (systems) outside of the die to the die, and conveying signals and currents within the die, such as from circuit element (e.g., transistor structure) to circuit element. The problems and challenges associated with each are similar in kind, but occur on a vastly different scale than one another.
For example, a semiconductor die will typically be mounted to some sort of leadframe or substrate having conductive fingers or traces, respectively, on the order of one or a few thousandths of an inch (bond wires are included in this perspective). Within the die, however, the conductive lines formed on the die tend to be on the order of one micron (.mu.m). Each of these current and signal conveying milieus, is bound (limited) by its own unique set of limitations.
For example, conductive fingers on leadframes and conductive traces on substrates for mounting semiconductor dies suffer, generally, from the inability to achieve a relatively fine pitch. In other words, it is difficult to achieve a close spacing of small conductors, especially in the vicinity of a die-receiving area, even if the conductors fan-out from the die-receiving area.
Vis-a-vis conductive lines on the die itself, there are problems associated with the very large number of conductive lines required to interconnect the vast number of circuit elements formed on the die, and although it is feasible to construct lines with widths less than one micron, such finer-and-finer lines are simply incapable of carrying much current, and exhibit adverse parasitic characteristics.
As is known, the resistance exhibited by a conductive line is a function of the resistivity and cross-sectional area of the conductive material of the conductor. Present day semiconductor fabrication processes already allow the reliable formation of metal (e.g., aluminum) lines having a width (as measured across the surface of the semiconductor die) on the order of 0.5-0.7 .mu.m, and the formation of poly (polysilicon) lines having a width on the order of 0.5-0.6 .mu.m. Seemingly already small, it has been the object of prolonged endeavor to make conductive lines on a die even smaller. Coupled with certain limitations on the ability to form thick lines, the cross-sectional area of the lines is become ever smaller. This can be disadvantageous, since high current densities (on the order of 10.sup.6 Amps/cm.sup.2) will cause a conductor to exhibit significant electromigration of atoms from one end of the line towards the other end of the line, which may result in catastrophic thinning or voiding of the line.
Generally, the present invention addresses a range of concerns in the design and fabrication of semiconductor integrated circuit (IC) devices. Present efforts are generally directed to the complementary goals of decreased circuit size and/or higher circuit density. These goals are generally achieved by providing smaller circuit elements (e.g., transistor structures), and/or by placing greater numbers of these elements on a given semiconductor die (chip). These trends are evidenced in the design and fabrication of virtually all types of integrated circuits, including custom and semi-custom application-specific integrated circuits (ASICs), memory chips, logic chips, and other IC structures. These trends are fueled by a desire for (and a market demand for) integrated circuits of greater complexity and capability, and are made possible by recent advances in semiconductor fabrication equipment and processes.
In general, the transistor, in any of its several different forms (e.g., bipolar, MOS, and the like) is the basic building block of most modern ICs, and is incorporated into many elemental structures of modern digital integrated circuitry (e.g., logic circuits, memory cells, and the like). Very complex and capable circuitry is implemented by forming several, up to millions of, transistor structures on a single semiconductor die and connecting these transistor structures together (and/or to other elements formed on the semiconductor die) and/or fabricating additional circuit elements atop the transistor structures. Transistor structures are already being formed with overall dimensions as small as on the order of 20-40 .mu.m (microns) across (wide), and are expected to become even smaller as semiconductor fabrication processes improve.
In fabricating integrated circuits containing ever-greater numbers of ever-smaller transistor structures on a die, an ancillary need arises for processing techniques capable of providing more-and-more, smaller-and-smaller conductive lines on the die, for interconnecting ("wiring") the transistor structures to one another, and for connecting the circuitry on the die to Input/Output (I/O) bond pads on the die. Evidently, there is a need for a great many of these conductive lines on a given die. (For example, two or three lines per transistor.) Since these interconnecting conductive lines perform only a `passive` function (i.e., carrying signals and/or power to and from circuit elements), there is considerable pressure to make these conductive lines as small (fine, narrow) as possible so that they do not occupy and dominate valuable `real estate` (die surface area) that could be better used for `active` circuitry (i.e., for logic, switching, amplifying, etc.).
Typically, conductive lines on a semiconductor die are formed of conductive material such as a metal (e.g., aluminum, tungsten, or the like) or polysilicon ("poly", or doped polysilicon), or silicides (silicon-metal compounds).
As transistor size (and semiconductor feature size, in general) decreases, the currents which flow between circuits also tend to decrease. This limits, to some extent, the effect of higher resistance conductive lines (due to smaller size). However, maximizing the speed of integrated circuits remains a highly desirable goal. Higher resistance conductive lines contribute to on-chip wiring (conductive line) delays when combined with the effects of parasitic capacitances. The wiring resistance and the capacitances combine to form an R-C network which slows voltage waveforms, thereby slowing overall circuit performance. Evidently, keeping the resistance of conductive lines small would serve to improve circuit speed. However, the trend toward smaller circuits forces the size of conductive lines downward, thereby tending to increase their resistance per unit of length.
Although currents between transistors on an integrated circuit tend to decrease in magnitude with the size of the transistors, the currents required at the I/O pads of the integrated circuit generally do not decrease commensurately. In general, the same or similar current carrying capability is required at the "pins" (e.g., bond pads) of the integrated circuit, regardless of the circuit geometry. Inrush currents and high I/O currents can severely stress the current carrying capability of small conductors, causing them to "blow" like fuses in extreme cases.
As evidenced by the above discussion, what is needed are techniques of forming conductive lines on a semiconductor die which are extremely small, yet exhibit extremely low resistivity (i.e., high conductivity).
In recent years, new materials have been discovered which exhibit super-conductivity at relatively high temperatures. Examples of these materials are thallium and YBCO (yttrium barium copper oxide). Thallium films, for example, have been found to be useful in microwave and RF applications. Other materials and compounds will become available in the future, and are within the intended scope of the present invention.
Although it might seem that the use of superconductive materials for conductive lines on semiconductor dies is somewhat self-evident, the materials are extremely difficult to pattern, because, inter alia, of their inability to be etched with high resolution, high productivity plasma equipment. Neither the superconductors nor their component atoms form volatile compounds which can easily be removed. Wet etching is possible, but not easy, and the masking of high resolution lines is problematic (e.g., using photolithography techniques).
Another problem which surfaces when attempting to utilize superconductors in semiconductor device assemblies is the sensitivity of the superconductors to heat. Superconductive materials exhibit their superconductivity (essentially the absence of any resistive effect whatsoever) only below a certain critical temperature. Above this temperature, the superconductive materials cease to behave as superconductors, and often exhibit extremely high resistance (i.e., they become worse conductors of current than conventional conductive lines).
Superconductors have arbitrarily been divided into two main categories: high-temperature superconductors (HTS's) and low-temperature superconductors (LTS's). Low temperature superconductors are those which exhibit superconductivity only at temperatures below 30.degree. K. (Kelvin). High temperature superconductors are those which remain superconductive at temperatures above 30.degree. K. Some high-temperature superconductors, such as those based on Yttrium exhibit superconductivity at temperatures well over 100.degree. K. A problem that would be inherent in using superconductors on or near an operating semiconductor device is the often significant amount of heat generated by the device itself. Because of their sensitivity to heat, superconductors employed in conjunction with semiconductor device assemblies would appear to require some form of active (or other extensive) cooling, to prevent the superconductors from becoming non-superconductive (and highly resistive) when exposed to the heat generated by operating semiconductor devices. Techniques such as immersion in liquid nitrogen come immediately to mind to effect this cooling. However, even when superconductive structures are cooled with liquid nitrogen, a semiconductor device operating in close proximity to a high-temperature superconductor can cause portions of the superconductor to reach a temperature higher than its critical temperature, thereby causing the superconductor to exhibit localized high resistance. This would tend to limit the overall usefulness of superconductors, as it would impose stringent, in some cases impossible, limits on the power which could be dissipated in semiconductor device assemblies to lower power levels. This argues against the utility of using superconductors, in any form, in connection with high speed, high power semiconductor devices which could benefit greatly from the attributes of superconductors.
As used herein, the term "semiconductor device" preferably refers to a semiconductor die having circuit elements and conductive lines formed on a surface thereof, and the term "semiconductor device assembly" preferably refers to a semiconductor device mounted on, within or to a package element, such as to a leadframe. The term "leadframe" as used herein, includes usages that are broader than traditional sense of leadframes.
Other known problems addressed by the present invention are semiconductor circuit element failure due to over-current conditions (e.g., due to parasitic SCR latch-up ), and semiconductor circuit element failure due to overheating.